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To read the NAND, I also needed some PC software to control the FTDI lines. Luckily, there already is a library which supports all the nifty bitbang modes of the chip, including the host-bus-emulation mode needed here. I whipped up a small bit of software that'll try to autodetect the specific NAND installed and uses that info to set the parameters and algorithm to read out the chip. It does that by reading out the NAND page by page.
The software can read out a NAND quicker than my parallel port solution can, it'll get about 250KByte a second. That still is orders of magnitude below the maximum attainable speed of the FT2232H. The reason probably is because of latency: every time you switch from writing data to reading data, the chip will introduce a bit of latency because of how the USB bus works. Reading just one page at a time means the latency gets introduced fairly often, degrading performance. The software could be speeded up a lot by sending the read commands for multiple pages, then requesting the data read. For me, this was enough: the current software can read an 1GByte chip in about half an hour and that was the biggest chip I tested
I also wanted to build the ability to write a NAND chip in the software, but after some thought I decided to abandon it: I didn't need that feature myself, and writing a page to the NAND also means the OOB data for the page, containing e.g. the ECC-data, would have to be written. The ways to do ECC and the location to store that vary from device to device, and I wasn't willing to dive into that.